Friday, November 23, 2018

PIC32MZ/EF Pin Slew Rate Control

If you look very carefully at the PIC32MZ/EF processor data sheet you will find a few references to the ability to set individual pins Slew Rate. This functionality essentially changes the driver output current in several discrete levels. This then changes the achievable Slew Rate of the pin, or: “How fast the pin transitions from one logic level to another”. This is useful in controlling ringing on traces and meeting EMI emissions requirements.

While FPGA’s have Slew Rate control on nearly all their output pins, the PIC32MZ/EF only has this available on selected pins.

Two registers attached to the port registers control the Slew Rate of the selected pin and each pin can be set independently of the others.

The Slew Rate control registers are,

    SRCON0x, SRCON1x

Where ‘x’ is the port letter designation (A, B, C … K)

Figure 1: Section 12:2 of the PIC32MZ/EF data sheet gives a brief description of the Slew Rate functionality. Also note that the table lists: Slowest, Slow, Medium and Fastest – yet the enumerations in Harmony list these as: Slowest, Slow, Fast and Fastest. Showing just how hard it is to keep ‘comments’ and ‘code’ synchronized, using the same terms!

To find the ports/pins that allow this control, search the data sheet for: ‘SRCON0A’, B, C, etc… This should take you to the tables in section 12.5 of the data sheet titled: “I/O Ports Control Registers” (Be careful that you are looking at the proper table for the exact package of the device you are using). The SRCONx bits are currently listed at the bottom of each port register table.

The port pins that allow Slew Rate control on a PIC32MZxxxxEFx064, a 64 pin device can thus be found as follows,

    Port B: RB14, RB10, RB9, RB8 RB5 and RB3
    Port C: No pins
    Port D: No Pins
    Port E: RE3, RE2, RE1, RE0
    Port F: RF1, RF0
    Port G: RG9, RG6
Similar lists can be quickly made for the other package types.

It can be seen that this is not every pin in the PIC32MZ/EF-064 device. So what is the logic here?

#1 – There are a few high speed, 50 MHz SPI ports available on this device and they have specific requirements of what pins must be used for high speed operation.

    • 50 MHz Max on SPI2: Pins RB3 &RB5
    • 50 MHz Max on SPI3: Pins RB10, RB9 & RF0

    These Fast SPI pins are all Slew Rate controllable

#2 – The REFCLKOx pins can be mapped to Slew Rate controllable pins.

#3 – In PIC32 devices that include a DDR SDRAM interface, the drive strength of that interface is also controllable as a whole. See the Harmony enumeration: “DDR_PHY_DRIVE_STRENGTH”.

Controlling the Pin Slew Rate

There are several Harmony 2.x functions available to control the Slew Rate of the pins.

Note: See Harmony Help for exact details on using these functions.

* See if the Slew Rate functionality even exists for your PIC32 device,

* Get the current Slew Rate setting of a port pin,

* Set the Slew Rate for a pin or a group of pins on a port (i.e. Channel),

The Slew Rate is specified as one of the following enumerations,

The ‘channelMask’ is a UINT16 that has a ‘1’ in the pins bit position for the pin you want to change, otherwise the pins strength remains the same and is not changed.

For example, to set just RB3 to the ‘Slow’ Slew Rate,

To Set pins B3 and B5 to the ‘Fast’ Slew Rate,

The various PLIB functions above must be called manually in your PIC32 Project as there are currently no Harmony Configuration Settings for the pins Slew Rates.

This is easy enough to do with a ‘Standard’ Harmony Application in the App_Initilize() function as shown in Snippet 1 below.

Snippet 1 – An example showing how to set an individual pin to a selected Slew Rate in the Harmony App_Initialize() function, this function is located in the file App.c.

What Does Each Setting Do?

The PIC32MZ/EF data sheet is a little vague on the exact nature of the various Slew Rate setting, so I made some measurements on one of my proto boards.

First thing is to compare a normal pin with a Slew Rate controllable pin. Note that the default Pin Slew Rate is set to Fastest for the Slew Rate controllable pins (See the note on the bottom of figure 1).

Using a standard CMOS loading test circuit [1], I measured a normal pin and a Slew Rate controllable pin, a plot is shown in figure 2 and 3. The various Slew Rate settings of a fast pin are shown in figure 4. Table 1 summarizes all the results.

Figure 2 – Rise time comparison of a normal pin and a Slew Rate controllable pin at their fastest settings.


Figure 3 – Fall time comparison of a normal pin and a Slew Rate controllable pin at their default settings.

Figure 4 – Effects of the various Slew Rate Settings applied to a test pin.


Table 1 – Tabulated Slew Rates of the various Pin types and Slew rate settings.

Wrapping It Up

The Overshoot seen in the figures at the fastest pin Slew Rate setting is undoubtedly a result of my test fixture being less than optimal. Normally the Oscilloscope probe would be located very close to the devices driving pin to minimize the parasitic inductance of the trace. In my ‘Quick-N-Dirty’ test jig, I used a MINI32MZ PIC-On-A-Stick module, this interfaced to one of my own breakout boards. The length of the trace from the PIC32 pin to my Oscilloscope probe is approaching 1 inch and even worse for a fast pules is the 0.1” header strip that the pulse has to traverse from the PIC32MZ to my breakout board and test load. These header strips add quite a lot of inductance to the overall path.

This, through leads to a great demonstration of why Slew Rate control adjustments are so useful in digital applications. My less than perfect test fixture is a ‘real’ PCB and I have seen much worse designs than what I had, still look at the amplitude of that ring I was able to make in just an inch!

In the fastest setting shown in figure 4 that little, high frequency ‘ring’ can cause all sorts of EMI emissions issues. In the worst case the ringing can be so bad as show up on the leading edge of the pulse, or be so high in amplitude to possibly cause double clocking.  This is why the PIC32 devices that have an external DDR SDRAM interface have Slew Rate controls on all the pins associated with those ports. It is much easier to set the output pin Slew Rate to control EMI and ringing than to add, then adjust, a bunch of series resistors in each output line on a PCB to control the rise time and overshoot problems.

[1] The standard CMOS loading circuit is 15pF in parallel with 1 Megaohm to ground. The measured rise time of the Oscilloscope used was 1.2 nSec. The Oscilloscope rise time was not corrected for in the rise time plots. It is corrected as noted in the tabular results.

Article By: Steve Hageman

We design custom: Analog, RF and Embedded systems for a wide variety of industrial and commercial clients. Please feel free to contact us if we can help on your next project.

Note: This Blog does not use cookies (other than the edible ones).

No comments:

Post a Comment