ATMEL UC3 32 Bit Processors and GCC Compiler Optimization - Part 2 - Timing
To test the ATMEL GCC Compiler Optimization with respect to loop and IO timing I wrote a simple little SPI type data output routine that simulates bit/bang IO with high level ASF commands. Specifically I wrote a little function that takes a data value, shifts it and actuates a clock pin. The usual thing one does for bit bang IO.
Figure 1 - Here is the code that I used to simulate a Bit/Bang SPI routine, very basic. I used a high level “ioport” command from the ASF framework to set the pins, just to see how fast this ASF method could be.
I set the ATMEL EVK1104 Eval Board to a 66 MHz Internal Clock Frequency and just called the spi_test() routine from a number of places in a simple main.c program, this was to prevent the function from getting inline optimized out. I also made sure that the variable spi_data was not optimized away by making it dynamic in all the calls and by defining it in the main program as volatile.
Now for the results of this test. As can be seen from Figure 2, no optimization is a pretty bad idea for a program such as this as the clock was measured in kHz, not MHz! All the other optimizations had about the same speed increase (within 1% or in the 10's of nSeconds of each other).
Figure 2 - As can be seen in the data, no optimization is a pretty bad idea when doing bit bang IO if you want any speed at all. Using a 66 MHz CPU core clock the SPI clock speed came out a respectable 2.7 MHz when optimized, not blindingly fast, but fast enough - and this was using the high level ASF commands to bang the pins around with.
All the optimizations have some issues: In debugging or in the way the code may or may not actually work, so it is best to study some of the options first before you commit to actual plans.
The code was compiled in AVR Studio 6 that was current on 6Jun12.